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Extra info for Caesar, II, Civil Wars (Loeb Classical Library)

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Figure 2-7 Sequence of Events [Example 2-1] illustrates a simple method of embedding an event directly into the Verilog RTL. The Verification Process 27 Example 2-1 `ifdef EVENT_MONITOR_ON // Detects when queue is full // and queue write request occur simultaneously always @ (c_q_full or c_q_write) begin @ (negedge ck) begin if(c_q_full & c_q_write) $display(" EVENT%0d:%t:%m", `EV_Q_FULL_WR, $time); end end `endif An alternative solution to embedding the event monitor's detection and reporting code directly into the RTL would be to encapsulate the event monitor in a module.

This permits the creation of multiple assertion libraries optimized for specific verification processes within the flow. For example, we might create an assertion library optimized for formal verification that contains either vendor specific model checking meta-comments or a library that implements a state machine to trap illegal temporal behavior. Similarly, we could create a simulation-targeted assertion library, which logs events to be post-processed and analyzed for correctness. , an event that must always occur) assert-eventually-- an event triggered window, bounding a check for a liveness property violation assert-eventually- always--an event triggered window, bounding a check for a liveness property violation (once the property occurs, it must remain valid until the ending event-trigger or the end of simulation occurs) assert-one-hot-- a check for one hot encoding violations By setting the Event 1 expression to 1 and the Event 2 expression to 0 in our instantiated assertion checkers, the event-triggered window is enabled for all time.

This page intentionally left blank. 3 RTL Methodology Basics Recent productivity gains in a designer's ability to generate gates have stemmed from the advances and widespread acceptance of synthesis technology into today's design flows. In fact, design productivity has risen tenfold since the late 1980s, to over 140 gates per day in the late 1990s. Unfortunately, design verification engineers are currently able to verify only the RTL equivalent of approximately 100 gates per day. Moreover, designers must now comprehend the relationships, dependencies and interactive complexity associated with a larger set of functional objects, all resulting from the productivity gains of synthesis.

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