Download e-book for kindle: CMOS Integrated Switching Power Converters: A Structured by Gerard Villar Piqué

By Gerard Villar Piqué

This e-book describes the dependent layout and optimization of effective, power processing built-in circuits. The strategy is multidisciplinary, masking the monolithic integration of IC layout innovations, energy electronics and regulate conception. specifically, this publication permits readers to conceive, synthesize, layout and enforce built-in circuits with high-density high-efficiency on-chip switching energy regulators. themes coated surround the dependent layout of the on-chip energy offer, potency optimization, IC-compatible strength inductors and capacitors, strength MOSFET switches and effective change drivers in normal CMOS applied sciences.

  • Provides a finished reference on dependent layout and optimization of totally monolithic strength offers for on-chip energy administration;
  • Describes a multidisciplinary process, encompassing better built-in energy units, either lively and reactive, in addition to complex circuit topologies and switching keep watch over tools, including their implementation;
  • Enables concurrent layout of compact adaptive strength provides, including system-level and circuit-level techniques.

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Additional info for CMOS Integrated Switching Power Converters: A Structured Design Approach

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Applied gate voltages at the 3-level converter transistors, during their on-state (a black dot indicates that the particular transistor is off) . . . 25 µm mixed-signal process) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-level converter optimized design main characteristics, referred to Io = 100 mA . . . . . . . . . . . . . . . . . . . . . . . . . 3-level converter selected design main characteristics, referred to Io = 100 mA . .

Power MOSFETs switching current values of the 3-level Buck converter, for both operating modes (the black dots indicate those situations where the transistor does not switch) . . . . . . . . . . . Applied gate voltages at the 3-level converter transistors, during their on-state (a black dot indicates that the particular transistor is off) . . . 25 µm mixed-signal process) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-level converter optimized design main characteristics, referred to Io = 100 mA .

Buck converter optimized design main characteristics . . . . . . . . Inductor optimized design characteristics . . . . . . . . . . . . . Output capacitor optimized design characteristics . . . . . . . . . . Buck converter power switches optimized design characteristics . . . Compared converters main parameters . . . . . . . . . . . . . . v A and v B values along the four different converter states (large C x capacitor is considered) .

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